• SCIENTIST/ENGINEER,

IBM Corporation, Austin, TX: Verify the logical design of future POWER and System Z processors, cache and memory hierarchy, and full systems. Create environments and methodologies for simulating VHDL input, analysis, and problem debugging. Perform functional and performance verification of POWER server microprocessors. Work on novel POWER9 architecture, OpenPOWER innovation, and OpenCAPI innovation. Develop C++ test, test bench, drivers, and monitors to verify CPU's. Develop and validate test plans for different CPU units. Debug RTL, simulate HDL designs, and test environments. Manage and coordinate C++ coding, debugging, test plan reviews, and functional coverage requirements between unit/system teams. Work on Nest Memory Management Unit, PowerBus, and CPU Fabric Link Layer verification. Verify on-chip accelerators MMU Radix/HPT translations for single/multi-threads, TLB/SLB Cache - coherence, Cache/IO acceleration, MMU performance, and CPU Fabric Link Layer. Utilize: imulation and debug logic designs, HDL Logic design skills in VHDL or Verilog/SystemVerilog, Microprocessor Architecture, Functional/Logic verification of SOC's, Interconnects and Bus protocols, verification methodologies and tools, and Program/Project management skills. Required: Master's degree or equivalent in Electrical Engineering or related (employer will accept a Bachelor's degree plus five (5) years of progressive experience in lieu of a Master's degree) and one (1) year of experience as a Design Engineer II/Program Manager or related. One (1) year of experience must include utilizing Simulation and debug logic designs, HDL Logic design skills in VHDL or Verilog/SystemVerilog, Microprocessor Architecture, Functional/Logic verification of SOC's, Interconnects and Bus protocols, verification methodologies and tools, and Program/Project management skills. Send resumes to IBM, box #V340, 71 Fifth Avenue, 5th Floor, New York, NY 10003.
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PostedMay 16, 2017